Modern microprocessors typically include a central processing unit (CPU) and a memory controller for controlling accesses to and from main memory. Most main memory in modern computer systems is double data rate (DDR) dynamic random access memory (DRAM) that conforms to standards set forth by the Joint Electron Devices Engineering Councils (JEDEC). The original DDR standard was published in 2000 and has over time been enhanced to include standards known as DDR2, DDR3, and DDR4.
The JEDEC standard interface specifies that during a read operation, the DDR DRAM will issue DQ (data) and DQS (data strobe) signals at the same time, a manner commonly referred to as “edge aligned.” in order for the DRAM controller to correctly acquire the data being sent from the DDR DRAM, the DRAM controller typically utilizes delay-locked loop (DLL) circuits to delay the DQS signal so that it can be used to correctly latch the DQ signals. Topological and electrical difference between DQ and DQS interconnects result in timing skew between these signals, making it important to establish a proper delay for the DLL. For similar reasons, the DRAM controller also utilizes DLL circuits to support the writing of data to the DDR DRAM.
The timing delays needed by the DLL circuits will vary based on board layout and operating conditions and so are customized for each design configuration each time the device is turned on by executing a training program. The training program is typically a software program stored in a basic input/output system (BIOS) memory device, but it can also be implemented within the device hardware. The training program executes an algorithm to determine appropriate timing delays associated with each memory interface signal.
Moreover, memory chips now operate at far higher speeds than the speeds of the original DDR DRAMs. For example, the DDR4 standard now specifies operation at 1600 MHz, 1866 MHz, and 2133 MHz. At these extremely high speeds, skew between signals becomes significant and difficult to train. The DDR4 standard has added features to facilitate signal training, including command and address training. For example, DDR4 DRAMs perform parity checks on command and address signals and activate an alert signal in response to detecting a parity error. However these features require two extra pins on the microprocessor and thus add to product cost.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect connection as well.